European Processor Initiative (EPI): what is and why be part of it
The importance of high-performance computing is constantly increasing and growing. Industry reports show that annual global IP traffic will soon reach several zettabytes (ZB): large amounts of new devices collect and store data and scientists are exploring new computing approaches for solving global challenges. The need to collect and efficiently and timely process that vast amount of data comes at a price. We are now in the “Era of Exascale Computing”: the existing approach to HPC systems design is no longer sustainable for the exascale era (exascale systems being defined as those capable of executing 1018 calculations per second).
Energy efficiency is of enormous importance for the sustainability of future exascale HPC systems. The importance of sustainable high-performance computing has been recognized by the European Commission that has strategically initiated efforts to achieve and support activities towards the implementation of European exascale computing systems and related technologies.
EU efforts are synchronized in the establishment of the EuroHPC Joint Undertaking, a legal funding entity that will enable pooling of national and European Union (EU)-wide resources in high-performance computing to acquire, build and deploy the most powerful supercomputers in the world within Europe. The European Processor Initiative (EPI) project is one of the cornerstones of this EU HPC strategic plan. This project is currently implemented under the first stage of the Framework Partnership Agreement signed by the Consortium with the European Commission (FPA: 800928), whose aim is to design and implement a roadmap for a new family of low-power European processors for extreme-scale computing, high-performance Big-Data and a range of emerging applications.
The purpose of the EPI project is to design and manufacture a high performance and low consumption processor, by implementing vector instructions and specific accelerators, such as accelerators for AI, with high memory bandwidth.
The design will exploit results obtained through intensive use of simulation, development of a complete software stack, and the use of the most advanced semiconductors.
Finally, EPI’s goal is to develop European know-how on design and realization of the chips for high-performance computing, allowing an independence and autonomy of Europe from American and Asian high-tech companies.
The chips designed from EPI will be built by SiPearl, a company chosen by the consortium for the patent registration and the go-to-market.
The first EPI phase started in December 2018 and all the main activities of the project are currently well underway. EPI will ensure that the key competency of high-end chip design remains in Europe, making available to scientific leadership, industries, engineers and European know-how the access to the developed technologies.
The design of a new family of HPC processors cannot be sustainable without thinking about possible additional markets that could support these activities in the long term. Therefore, EPI will cover other areas such as the automotive sector, ensuring the overall economic viability of the initiative.
EPI will use a holistic approach to define the system architecture and its components and to develop:
• Hardware platform architecture and components
• software system and runtime (OS, middleware, developer kits, libraries, etc.)
• applications for end-users of various domains, not limited to traditional HPC
To achieve its objectives EPI will develop:
• a new low consumption system processing unit optimized for the exascale HPC
• an accelerator, to increase energy efficiency in high computing intensity activities such as HPC, artificial intelligence (AI), automotive and many other application domains
• an automotive demonstration platform, to test the relevance of previous components in this industry
EPI activities are organized into three high-level technology domains and two global domains (these last for the integration and coordination of the first ones). These five domains are called “Streams”.
The three high-level technology domains are:
GPP Stream (General Purpose Processor): GPP Stream refers to a wide range of common technologies across different application domains. They include a selection of cutting-edge process technologies:
- massive parallelism with multi-cores
- a memory hierarchy with High Bandwidth Memories (HBM) integrated using a silicon interposer
- a chiplet approach with a high-speed link between silicon dies
- a low-power design approach with low-voltage operating point and fine-grain power management, built-in security to isolate applications and resist against the new cyber threats’ environment.
The software stack will be designed to integrate and take advantage of these features to achieve high-energy efficiency and maximize performance across a wide range of layers from the low-level firmware, all the way up to system software and application run-times.
General purpose processor (GPP) stream is focused on the creation of the first implementation of a processor platform targeting the HPC market.
Accelerator Stream: The Accelerator stream will develop and demonstrate fully European processor IPs based on the RISC-V Instruction Set Architecture, providing power efficient and high throughput accelerator tiles within the GPP chip. Using RISC-V allows leveraging open-source resources at the hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.
Automotive Stream: The Automotive stream activities are targeting main trends driving innovation in the automotive industry including the introduction of autonomous driving (levels 4/5) and the Connected Car infrastructure. Within this stream, HPC general-purpose processors and HPC accelerators will be integrated into the architectural solutions for a novel embedded high- performance computing (eHPC) platform to demonstrate the approach to be technologically, functionally and economically successful.
The two global domains are:
Global Technical Stream: it addresses global EPI architecture, co-design methodology, architectural explorations, system and management HW/SW and simulation, and modeling tools for benchmarking and validation.
Coordination Stream: as its name implies, it is focused on the coordination of the whole project.
All the activities within these streams are deeply interdependent and therefore the interaction of all activities is crucial for success of the initiative.
Exascale computation systems need to simultaneously meet challenges related to performance, system cost, and energy efficiency. To deliver performance, a vast amount of resources is required, but the wrong choices of components, architecture, or implementation might result in a system that is too expensive and/or too power-hungry. To find the right balance, global system-level optimization is necessary.
In the next article dedicated to EPI, we will get to the heart of the more technical issues, describing a common platform for the management of power and security (CP), the RISC-V architecture and the project roadmap up to 2024 and beyond!