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The debate is getting hotter and hotter: ARM or RISC-V? ARM and RISC-V? Are ARM and RISC-V competitors or synergic?
When talking about processors, the most important factor to consider is the instruction set architecture, or ISA. This is because programs developed by software engineers will only be able to operate on specifics ISAs unless the code is written using an interpreted language that is cross-platform (such as Python or Java). There are many ISAs available to designers. With regards to large processing systems such as HPC systems and clusters, the two ISAs most widely used are x86/x64 and ARM.
Intel developed the x86/x64 architecture since the 1970s and since then it has been the industry workhorse, while the ARM architecture was developed in the late 1980s initially for use on smaller systems. The major difference between the two architectures is that x86/x64 is a complex instruction set (CISC) with many advanced features while ARM is a reduced instruction set (RISC), that only has a handful of instructions by comparison. CISC allows for a computer to do more in a single instruction cycle while RISC allows for simpler programming. Generally speaking, RISC requires more clock cycles to complete the same instruction in CISC, but can do so more efficiently (energy-wise) which makes them ideal for mobile applications.
ARM is the most successful RISC architecture on the planet, with its licensees shipping billions of chips a year and is the dominant CPU architecture for microcontrollers, microprocessors, and mobile systems, and is increasing its footprint in HPC.
While x86/x64 and ARM are the dominant architecture in the heavy processing market, they may face serious competition from a new processor architecture: RISC-V.
Emerging in 2010 from the Parallel Computing Lab at UC Berkeley in California, RISC-V is a modular architecture that allows developers to build whatever they desire on top of the core instruction set.
While x86/x64 may look at ARM and RISC-V from a comfortable (dominant) position, ARM may feel the competition of RISC-V. For both the ARM and RISC-V Instruction Set Architectures significant efforts are being made to establish them in the area of high-performance computing. What are the major differences between RISC-V and ARM, and will one win over the other?
|Based on proprietary IP, and the companies license their products||Royalty-free specification architecture|
|Relatively small number of processor vendors||Open-source RISC-V based cores are available, and there are also commercially licensed cores|
|Extremely large online community, support structure, and libraries to help designers target many different platforms including microcontrollers, microprocessors, and servers||As RISC-V is a relatively new Instruction Set, it’s still growing in terms of support for software and programming environments|
|ARM has teams of engineers developing hardware systems that make it easy for designers to incorporate ARM CPUs||While designers can experiment and develop RISC-V systems for free, there is little to no support for hardware design|
|ARM, being proprietary, can be export blocked by governments (such as when the US attempted to block the sale of ARM IP to China).||RISC-V is open-source and available for anyone with an internet connection to look up the standard and implement their own design.|
|OP-TEE is an open source trusted execution environment (TEE) implementing the ARM TrustZone technology.||RISC-V MultiZone security software model is small, and therefore faster. Several security mechanisms are built into RISC-V, including four levels of privilege rings, secure interrupt processing, and a unique physical memory protection (PMP) mechanism. Commercially available security enhancements are also available for RISC-V, including cryptographic libraries, roots of trust, and multi-domain TEEs.|
|ARM supports a number of macro-op fusion operations in their recent microarchitectures. Micro-operation fusing merges two instructions into one inside the processor, effectively implementing predicated execution without the instruction set’s help.||The basic RISC-V instruction set does not support predicated execution. However, the experimental BOOMv3 out-of-order speculative RISC-V processor uses a combination of a reduced instruction set with micro-operation fusing to implement predicated execution.|
|ARM, RISC-V support virtualization of CPUs and memory.||RISC-V supports the virtualization of memory using multi-stage page tables. Also, RISC-V implements identical page table entry formats for both guest and host tables. The RISC-V ISA does not currently support the virtualization of I/Os. I/O virtualization will mostly be a feature of the IOMMU and the platform-level interrupt controller (PLIC), which lies outside the domain of the RISC-V ISA to specify. The PLIC, as currently specified, does not include registers for configuring the injection of interrupts.|
|The ARM virtualization extensions enable hardware to virtualize a CPU using a hypervisor. Multiple operating systems can be run on each of the virtual CPUs.||The RISC-V H (hypervisor) extension v0.6.1 introduces a full duplicate of the CPU state: one copy for the guest and one copy for the host (similar to Intel VT-x). RISC-V supports the virtualization of CPUs by making sensitive registers and instructions privileged to host mode. As seen from the pre-release version number, RISC-V virtualization is a work in process. The first public implementation and evaluation was recently published of the latest version of the RISC-V hypervisor extension in a Rocket chip core for use in embedded systems.|
|While ARM was not initially designed to use custom extensions, that is changing, and the ARM ecosystem is beginning to employ custom extensions.||The RISC-V ISA is organized into groups of instructions (the base ISA & standard extensions). The ability to use extensions to the standard ISA can provide support for specific applications. For example, the recently released RISC-V Vector extension (RVV) enables processor cores based on the RISC-V ISA to process data arrays alongside traditional scalar operations to accelerate the computation of single instruction streams on large data sets|
It is worth underlying that a very significant difference between ARM, and RISC-V is in the business models. ARM is based on proprietary IP, and the companies sell and/or license their products. RISC-V is an open specification and platform; it is not an open-source only processor. Open-source RISC-V cores are available, as well as there are also commercially licensed cores.
Will RISC-V overtake ARM in the future?
If ARM is to survive the competition posed by RISC-V, it will have to rely on its overwhelmingly large market share (with respect to RISC-V) to present itself as a better choice for designers. While this tactic works for Intel, it may not do for ARM because of the reasons listed above.
The use of RISC-V is increasing, and there are signs that major companies are already looking at alternatives to ARM, and the attempted purchase of ARM by NVIDIA does not help this.
As technology continues to improve and support for RISC-V increases, designers will be left with the option between a paid-for processor architecture or a free architecture with no limitations. However, just because something is free does not mean it will take lead. The Linux operating system is a classic example; while most distributions are free, Linux makes up a tiny percentage of operating systems around the world.
E4 provides support to users in the selection of the ISA.
E4 bears to the market an extensive and unique know-how in ARM and RISC-V. E4 has designed its first Arm-based cluster in 2012 (https://www.hpcwire.com/off-the-wire/cineca-e4-announce-the-successful-conclusion-of-phase-i-evaluation-of-arm-clusters/) and presented the ARKA cluster, featuring ARM64+GPU+InfiniBand at the GPU Technology Conference 2015. (https://insidehpc.com/2015/05/e4-arka-arm64gpuib-is-now-here/). Within the PRACE-3IP Pre-Commercial Procurement for Whole-System Design for Energy Efficient HPC, E4 developed a liquid-cooled, ARM-based cluster configured with 8 nodes (Cosimo, non mi ricordo il # dei nodi…). E4 is currently hosting in its R&D Laboratories ARMIDA (ARM Infrastructure for the Development of Applications), an 8-node cluster based on Marvell TX2, where different components (GPUs, FPGA, I/O interfaces) can be tested and validated. E4 is currently integrating a cluster based on SiFive’s HiFive Unmatched processor. HiFive Unmatched ushers in a new era of RISC-V Linux development with a platform in a standard form factor. HiFive Unmatched is powered by the SiFive Freedom U740, a high-performance multi-core, 64-bit dual-issue, superscalar RISC-V processor.
By providing access to both ARM and RISC-V architectures, E4 can support to its users and developers in extensively testing their applications and codes and provide guidance to find the best overall solution to their requirements.