The European Processor Initiative (EPI)

The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, is a project with 28 partners from 10 European countries, with the goal of making EU achieve independence in High Performance Computing (HPC) chip technologies and HPC infrastructure.

EPI objectives come from three major research and innovation domains namely General Purpose Processor (GPP), Accelerator (EPAC) and Automotive with numerous common activities being shared across all domains. E4 and ST-I as Italian industries and Università di Bologna and Università di Pisa as Italian universities actively participated in project with completing roles and deliverables. E4 was tasked to develop the Test Chip Daughter Board in support of the EPI accelerator and the Intermediate Bus Connector in support of the General Purpose Processor.

The Accelerator (EPAC)

The EPI accelerator stream set out to deliver energy-efficient acceleration for high-performance computing and artificial intelligence workloads. With the European Processor Accelerators (EPAC) Test Chip proof of concept, EPI has demonstrated that it is possible to create an exclusively European design, while the use of open-source ISAs gives freedom from proprietary licences and export restrictions. The EPAC systems and FPGA software development vehicles make full use of the Linux OS and contribute to the community with patches, device drivers, and additional functionality to popular open-source HPC software packages such as OpenMP and MPI. Furthermore, parts of the hardware such as the STX (stencil/tensor accelerator) were developed using a permissively licensed open-source approach around the PULP platform.

In the following picture, Cosimo Gianfreda (right), CTO of E4 Computer Engineering, holds the box with two Test Chips, and Fabrizio Magugliani (left), Management of European Projects, holds the Test Chip Daughter Board.

The General-Purpose Processor (GPP)

The first generation of the EPI General-Purpose Processor (GPP), codenamed Rhea, will integrate technologies by EPI partners as well as unique features in terms of security, memory architecture, memory bandwidth optimization and power management. Including 29 RISC-V cores on board, the Arm V1 Neoverse architecture will offer an effective solution for HPC applications with capability to be scaled and customizable. The architectural decisions were taken following a co-design methodology and by analyzing the performance of advanced IP’s. Scalable Network On Chip to enable high frequency, high bandwidth data transfers between cores, accelerators, IO’s and shared memory resources.

In the following picture, Andrea Bartolini from Università di Bologna, (left) holds the Light Reference Board, a prototype board used as a development vehicle for Rhea, and Fabrizio Magugliani (left), Management of European Projects, holds the box with two Test Chips.

E4 is proud to be part of such an interesting project and to have fulfilled its commitments.

EPI will continue in the next years and E4 will continue to contribute with its 20+ years of know-how in developing innovative and leading edge products.

To know more on EPI, go here!

To read the Press Release on the conclusion of the Phase One of the project click here!