Participation in major European Projects of the High Performance Computing and Artificial Intelligence worlds forms a fundamental part of our strategy. These projects bring valuable human resources and expertise, and give us access to a network of important national and international institutions and companies, with which we can co-design and co-develop highly innovative solutions to be later replicated on the market.
The main entity financing and sustaining a large part of these projects is the European High Performance Computing Joint Undertaking (EuroHPC JU), headquartered in Luxemburg. EuroHPC JU coordinates the efforts and manages the resources of various European Countries with the aim of making Europe the world leader in Supercomputing.
E4 is currently coinvolved with 10 projects supported by the EuroHPC JU.
The growing need to process extremely large data sets is one of the main drivers for building exascale HPC systems today. However, the flat storage hierarchies found in classic HPC architectures no longer satisfy the performance requirements of modern data-processing applications.
ADMIRE‘s main objective is to establish a control mechanism by creating an active I/O stack that dynamically adjusts computation and storage requirements through intelligent global coordination, malleability of computation and I/O, and scheduling of storage resources up all levels of the storage hierarchy. To achieve this, the project will develop a software-defined framework based on the principles of scalable monitoring and control, separated control and data paths, and orchestrating key system components and applications through embedded control points.
Within this project, E4 is developing Software Heritage (SH) applications and tests, distributing and profiling SH, and providing ADMIRE’s partners with access to Cluster ARMIDA.
Random Power exploits the quantum properties of semiconductors to generate a practically infinite stream of random bits which power information security systems. In ATTRACT phase 1 the consortium, formed of two research centres and two societies, designed, produced, commissioned and fully qualified a small form factor card with an embedded bit generator.
Now, the consortium includes RaP!, a spin-off of original partners, and has been expanded to integrate teams with complimentary knowledge and expertise from other ATTRACT projects and beyond, with the aim of developing a True Random Bit Generator platform.
E4’s role is to develop and implement a Randomness Farm: the Randomness Farm is based on hardware that incorporates more generators into the infrastructure, with a scalable architecture. The hardware is complete with personalised software development to guarantee safe transmission of the bitstream, advanced functionality in real time and a suite of services to maximise adoption of the technology.
DYNAMOS develops fast (1 ns) and widely tunable (>110 nm) lasers, energy-efficient (~ fJ/bit), broadband (100 GHz) electro-optic modulators, and high-speed (1 ns) broadcast-and-select packet switches as photonic integrated circuits (PICs). DYNAMOS meets the expected outcome objectives and call scope by proposing the development of low energy (few pJ/bit) PICs, which are integrated into modular and scalable subsystems, and subsequently utilized to demonstrate novel data centre networks with highly deterministic sub-microsecond latency to enable maximum congestion reduction, full bisection bandwidth (lower congestion) and guaranteed quality of service while reducing cost per Gbps.
The proposed network offers optical circuit switched reconfiguration and guaranteed (contentionless) full-bisection bandwidth, allowing any computational node to communicate to any other node at full-capacity. DYNAMOS co-develops the entire ecosystem of transceivers, switches and networks to boost overall performance and to reducing the total cost of data exchange, instead of focusing on the improvement of individual optical links or interfaces.
E4 is the “Network & system demonstrations” work leader. E4 will formalize the set of integration and demonstration activities in order to systematically showcase the ability of the devices, network architecture and control, technologies to deliver the goals of system-network scalability, network related energy efficiency, network latency, network throughout, distributed compute task performance. E4 will aim to combine the compute motherboards with the DYNAMOS interface card and optical switch.
The European Processor Initiative (EPI) is one of Europe’s leading projects. It’s objective is to achieve European strategic autonomy in HPC, chip technologies and infrastructures. The project has finished its first triennial phase (2018-2021), releasing avant-garde technologies for European sovereignty such as the Rhea General-Purpose Processor (GPP). EPI focuses on processor technologies based on ARM and RISC-V architectures.
E4 will design and construct the EPAC Test Chip Daughter Board PCI3, for the RHEA Reference Platform. Once this prototype is ready for development, E4 will continue to oversee its management and administration.
EUPEX ha l’obiettivo di sviluppare la prima piattaforma europea per HPC, raccogliendo e inteEUPEX’s objective is to develop the first European HPC platform, collecting and integrating European technologies for system architecture, processing, software, development tools and applications. The EUPEX platform will be open, scalable and flexible. EUPEX aims to sustain the lively emerging European entrepreneurial ecosystem of HPC technology, addressing the related sectors of Artificial Intelligence and Big Data Analytics. E4 will contribute to the design, construction and validation of the GPU blade, the construction of the GPP/GPU cluster and the co-design of the second-generation EPI processors.
Computational fluid dynamics (CFD) has become a mature technology in engineering design, making a strong contribution to competitiveness and sustainability in a wide range of industrial sectors (e.g. transport, energy production and disaster prevention). Its future growth depends predominantly on the parellel use of HPC architecture; however, this is currently being hampered by performance scaling bottlenecks.The ambitious project exaFOAM seeks to overcome these bottlenecks with the development and validation of a series of algorithmic enhancements. These enhancements will be developed along the entire CFD process chain (pre-processing, simulation, I/O, post-processing).
Within exaFOAM, E4 will be validating the performance micro-benchmarks of homogenous and heterogenous architectures. In addition, E4 will be analysing the capabilities and modelling the industrial use cases of relevant architectures.
Today, the digital revolution is having a dramatic impact on both the pharmaceutical industry and the healthcare system as a whole.
The use of machine learning, large scale simulations and big data analytics in the process of drug design and development offers an excellent opportunity for reducing investment risk and patenting time, and consequently shortening patient response time.
LIGA aims to integrate and co-design the best European open source components, together with European intellecutal property (development of which has already been co-financed by previous Horizon 2020 projects). It will support Europe in continuing to be the global leader in CADD (Computer-Aided Drug Design) solutions, leveraging the high-end supercomputers of today, and the exascale resources of tomorrow, whilst at the same time promoting European competition in this field. The project will improve CADD technology on the platform EXSCALATE, which is dedicated to drug discovery.
E4’s role within the project is requirements gathering from different interested parties, in particular HPC companies and centres, for the evolution of HPC systems and EuroHPC infrastructures.
Other roles include drawing up a configuration and integration plan for the Exascale CADD platform; expanding applications (e.g. Gromacs, Ligen) to address GPU clusters; improving energy efficiency using more accurate measures and developing cluster models.
Machine learning can help improve weather modelling in the face of the climate change threat. MAELSTROM was born from this vision, with the aim of improving European computer architecture in order to assess future impacts on the climate. In particular, it will propose projects for the construction of computer systems with practical capabilities and optimal energy efficiency. Additionally, it will propose software frameworks to optimise the usability and efficiency of machine learning training on a large scale, and for large scale machine learning applications configured for the meteorological and climate sciences. Within MAELSTROM, E4 is tasked with providing around twenty different hardware configurations (including accelerated platforms) for the development and testing of machine learning tools, as well as providing access to different architectures and storage technologies, whose configuration will be co-designed.
The MaX Centre of Excellence will clear the way for the transition to exascale technologies and beyond, making use of open source community codes that are both highly successful and widely used in quantum simulations of exascale materials, adopting a sustainable software development strategy to face the sudden technological interruptions projected in the coming years. Within MaX, E4 is creating a network of potential code users, gaining visibility in the materials science community, learning modern techniques for code optimisation and collecting detailed information on the capabilities of code on a large number of platforms.
REGALE seeks to pave the way for the use of next-generation HPC applications in exascale systems. To this end, the project is building a prototype system, with an open architecture, and incorporating into its system a raised level of sophistication, with the goal of equipping supercomputing systems with mechanisms and policies that enable the efficacious use of resources and the running of complex applications.
E4 will contribute to requirements gathering and to the co-designing of small scale prototypes for the development and testing of applications. Our systems will also be used as evaluation platforms, again on the small scale. Finally, E4 will embed a pulp-controller into the REGALE prototype for the management of consumables, in collaboration with the University of Bologna.
To achieve elevated performance and better energy efficiency in future exascale computing systems, it is necessary to bridge the technology gap.
TEXTAROSSA was born out of this vision, applying a co-design approach to heterogenous HPC solutions, supported by the integration and extension of IPs, programming models, and tools derived from European research projects run by their partners. The technologies developed by TEXTAROSSA will be tested on Integrated development vehicles (IDV), which mirror and extend architecture based on ARM64 from the European Processor Initiative and the OpenSequana testbed. To guide technological development and evaluate the impact of the proposed innovations, TEXTAROSSA will choose a number of representative HPC, HPDA and AI examples which cover demanding HPC domains such as kernels, high-energy physics (HEP), Oil & Gas, and climate models, as well as emerging domains such as High Performance Data Analytics (HPDA) and High Performance Artificial Intelligence (HPC-AI). E4 is tasked with developing a heterogenous IDV based on the ARM platform and accelerators such as FPGA.
TRISTAN’S overarching aim is to expand, mature and industrialize the European RISC-V ecosystem so that it is able to compete with existing commercial/proprietary alternatives. This will be achieved by leveraging the Open-Source community to gain in productivity and quality. This goal will be achieved by defining a European strategy for RISC-V based designs including the creation of a repository of industrial quality building blocks to be used for SoC designs in different application domains (e.g. automotive, industrial, etc.). The TRISTAN approach is holistic, covering both electronic design automation tools (EDA) and the full software stack. The broad consortium will expose a large number of engineers to RISC-V technology, which will further strengthen adoption. This ecosystem will ensure a European sovereign alternative to existing commercial/proprietary players.
E4 will develop a demonstrator based on commercial FPGA and a test chip. The demonstrator will be suitable for Industrial applications, featuring a small footprint RISCV and including system software. The test chip is built using the TRISTAN EDA methods. E4 plans to industrialize and make available as a standard product a follow-on version of the Industrial Prototype developed in the project.