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SC23: the experience of E4 on RISC-V for HPC
E4 will participate as a speaker in the Second International Workshop on RISC-V for HPC at SC23 in Denver.
The goal of this workshop, which is taking place at SC23 (Supercomputing) in Denver on Monday 13th of November, is to continue building the RISC-V community in HPC by sharing the benefits of this technology with industry scientists, tool developers and supercomputer operators.
The potential benefits that RISC-V can offer to HPC are numerous, and assuming the significant growth rate of this technology, as the decade progresses it is very likely that RISC-V will become increasingly relevant and widespread for HPC workloads.
This workshop aims to bring together those who are already trying to popularise RISC-V in the HPC field with the supercomputing community at large, by sharing architecture benefits, success stories and techniques.
Our CSO, Daniele Gregori, will provide a talk within this workshop by bringing an overview of the current generation Monte Cimone HPC system and by describing our work preparing for our next generation RISC-V HPC system.
What is Monte Cimone? It is a fully-operational multi-blade computer prototype and hardware-software test-bed based upon E4’s RV007 blade system which comprises of the SiFive Freedom U740 SoC, which is a double-precision capable multi-core, 64-bit RISC-V CPU.
Read more in the workshop programme.