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E4 Computer Engineering and BSC co-organise a Workshop on RISC-V at HIPEAC 2024
The Workshop co-organised with BSC – Barcelona Supercomputing Center on the state of the art and how to make RISC-V the architecture of choice for HPC applications.
RISC-V: the cornerstone ISA for the next generation of HPC infrastructures
RISC-V is unique, even revolutionary, because it is a free, open-source ISA to which software can be ported, hardware can be developed, and processors can be built without the cost of licensing proprietary ISAs and/or paying royalties.
The current rise of RISC-V coincides with the slowing of Moore’s Law, meaning that increases in total processing power no longer comes along with new fabrication technologies, with the explosive growth in machine learning and AI applications, demanding massive increases in processing power, and with the growing availability in the market of chips designed by different vendors.
There are currently many RISC-V based hardware products from different companies, and there are a variety of off-the-shelf, low-cost development boards as well as boards suitable for compute-intensive applications running standard Linux. The freedom to configure and customize the RISC-V ISA in accordance with the applications’ needs, including custom instructions, is one of its strongest appeals of RISC-V for compute-intensive applications, making the RISC-V ISA an attractive choice for an unprecedented number of use cases in HPC and AI, IoT, Virtual / Augmented Reality. The future will see an explosion of applications that are designed for RISC-V.
The workshop, co-organised by E4 Computer Engineering and BSC – Barcelona Supercomputing Center, will bring together researchers from different disciplines, representatives from industries, computer architects, developers of scientific applications and users to describe the state of the art and outline the paths to be taken by RISC-V to make it the preferred ISA for HPC applications.
Co-design is a tremendous opportunity for fostering collaborations among the developers of application, hardware architects, data centers and users. Co-design will impact all scales of computing from desktops to supercomputers because all these scales face similar challenges in performance, energy efficiency, concurrency, data movement and application’s programmability. For RISC-V in large HPC infrastructures, there will be additional challenges including scalability and reliability that are brought about by the extreme size of such systems.
The workshop will provide a lively discussion and present early experiences and use cases of HPC infrastructure powered by RISC-V platforms.
The full programme will follow soon.